1. Field of the Invention
The present invention relates to a circuit analyzing device, a circuit analyzing method, a program for causing a computer to execute operation of the device or the method, and a computer readable information recording medium storing the program. In particular, the present invention relates to a circuit analyzing device in which an efficiency method for testing a circuit operation delay in LSI circuit deign work, a circuit analyzing method, a program for causing a computer to execute operation of the device or the method, and a computer readable information recording medium storing the program.
2. The Related Art
Recently, in a large-scaled integrated circuit such as an LSI circuit which is indispensable for data analysis operation, various control operation or such in various industrial fields, a strict demand exists not only for high-grade circuit integration but also circuit operation timing. For this purpose, a signal delay time testing scheme (simulation) providing performance by which such circuit characteristics can be tested with a high accuracy is required.
In such an analysis for a signal delay time of a transistor circuit such as an LSI circuit, a time required by a circuit part (referred to as a ‘critical path’, hereinafter) which directly relates to a predetermined input/output item, from a timing of an application of a predetermined input value in an input terminal through a timing of an appearance of a predetermined output value from an output terminal is obtained. Upon carrying out such a circuit operation analysis, ‘carrying out predetermined operation of the relevant circuit part’ is referred to as ‘activation’ or ‘activating’ of the ‘active path’. Normally, in a large-scaled integrated circuit, various active paths exist in a single circuit, and, a problem may occur as to how to set states of peripheral circuit parts upon analyzing the relevant circuit part when a specific active path is activated.
In such a circuit analysis, a signal setting for an input which does not logically affect the activation of the active path is not required in the logic circuit operation analysis. In fact, in an LSI circuit in the related art, since a demand for an increase of operation speed has not been so strict, it has been possible to obtain an effective signal delay time value, i.e., a delay value, even without especially considering operation states of the peripheral circuit parts. However, in a very high speed LSI circuit with a clock frequency of 1 GHz or more, a difference between an actual signal propagation operation delay amount, i.e., a delay time occurring in an actual circuit and a delay value obtained from a simulation increases due to a difference in a signal setting of the peripheral circuit parts. As a result, it may become difficult to carry out signal propagation operation delay time analysis, i.e., delay analysis precisely in accordance with the actual circuit. Therefore, it is necessary to even consider operation states of the peripheral circuit parts when delay analysis of an active path is carried out with a high accuracy for a very high speed LSI circuit designing work.
That is, in a circuit deign analysis in the related art, a circuit part along an active path, for which signal propagation operation delay time calculation, i.e., delay calculation is directly carried out, is extracted, for example. The delay analysis is carried out only for the thus-extracted circuit part of the active path. In this way, a signal setting for the other peripheral circuit parts which may affect activation of the relevant active path is not especially considered. However, as mentioned above, in an actual circuit of a recent very high speed LSI circuit, a delay of the active path may be much affected by signal setting states of the peripheral circuit parts. Therefore, in the above-mentioned way of extracting the circuit path along the delay calculation target path, it may not be necessarily possible to obtain an accurate load which should be applied in response to the signal transition. Further, when the signal transition or states of the peripheral circuit parts have not been sufficiently considered, a load applied to the path is fixed, and thus, a deviation of a calculation result from the actual circuit tends to increase. Other than the above-mentioned way, there is a way of generating an activation pattern especially by focusing on the active path. In this method, an accurate delay calculation is available in comparison to the above-mentioned way of extracting the relevant circuit part. However, the accuracy may not be sufficiently high also in this way.
Japanese Laid-open Patent Applications Nos. 8-63499, 9-325981 and 2001-76020 disclose the related arts.